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Showing posts from June, 2023

UVM SEQUENCE ITEM - SEQUENCE - SEQUENCER

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 Let's understand what's UVM Seq item, Sequence & Sequencer in a brief way: Sequence item:  It holds the collection of variables (that is, inputs & outputs) Sequence: This is used to create series of sequence items (that is, more scenarios) Sequencer: To arbitrate the sequence to driver For more detailed explanation, you can watch the video I've shared below:

System Verilog Constraint Scenario: 3

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   Qn. Write a constraint to generate unique random numbers between 99 to 100. SAMPLE OUTPUT:                                                                      Here's the step-by-step  video  illustration to solve this constraint. 

System Verilog Constraint Scenario: 2

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Qn. Write a constraint to generate the pattern 0102030405       SAMPLE OUTPUT:                                                                                             Here's the step-by-step video illustration to solve this constraint.   

System Verilog Constraints Scenario: 1

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 Qn. Write a constraint to generate random values divisible by 5.                     SAMPLE OUTPUT:       Here's the step-by-step video illustration to solve this constraint.