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Check for PALINDROME of a String using SV

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 CODE: module tb; string s1 = "madam"; string s2; initial begin s2 = {<<8{s1}}; //Storing each character as 8-bits using Streaming Op. if(s1 == s2) $display("\n %s is a Palindrome \n", s1); else $display("\n %s is NOT a Palindrome \n", s1); end endmodule SAMPLE OUTPUT: With Different String match: module tb;   string s1 = "jolly";   string s2;   initial     begin       s2 = {<<8{s1}}; //Storing each character as 8-bits       $display("\nReversal of gn. string is: %s",s2);       if(s1 == s2)          $display("%s is a Palindrome \n", s1);       else          $display("(Given String)%s != %s(Reversed String)",s1,s2);       $display("Therefore, %s is NOT a Palindrome \n", s1);     end endmodule SAMPLE OUTPUT: You can buy me a coffee! https://www.buymeacoffee.com/ch...
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Constraint to generate 100 phone numbers, where the first three digits should be '982'

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  CODE:   class phone_number; rand int num[]; constraint ph_num_size {num.size() == 10;} constraint ph_num {foreach(num[i]) { (num[i]>= 0) && (num[i]<10); if(i == 0) num[i] == 9; if(i == 1) num[i] == 8; if(i == 2) num[i] == 2; } } function void display(); $write("Mobile No. is: \""); foreach(num[i]) begin $write("%0p",num[i]); end $write("\""); $write("\n"); endfunction endclass module jk; phone_number ph; initial begin ph = new(); repeat(100) begin ph.randomize(); ph.display(); //$display("size is: %0d",ph.num.size()); end end endmodule           SAMPLE OUTPUT:
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UVM SEQUENCE ITEM - SEQUENCE - SEQUENCER

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 Let's understand what's UVM Seq item, Sequence & Sequencer in a brief way: Sequence item:  It holds the collection of variables (that is, inputs & outputs) Sequence: This is used to create series of sequence items (that is, more scenarios) Sequencer: To arbitrate the sequence to driver For more detailed explanation, you can watch the video I've shared below:
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System Verilog Constraint Scenario: 3

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   Qn. Write a constraint to generate unique random numbers between 99 to 100. SAMPLE OUTPUT:                                                                      Here's the step-by-step  video  illustration to solve this constraint. 
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System Verilog Constraint Scenario: 2

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Qn. Write a constraint to generate the pattern 0102030405       SAMPLE OUTPUT:                                                                                             Here's the step-by-step video illustration to solve this constraint.   
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System Verilog Constraints Scenario: 1

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 Qn. Write a constraint to generate random values divisible by 5.                     SAMPLE OUTPUT:       Here's the step-by-step video illustration to solve this constraint.   
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